Comparisons of Synchronous-Clocking SFQ Adders : Frontiers of Superconductive ElectronicsTAKAGI, Naofumi; TANAKA, Masamitsu.IEICE transactions on electronics. 2010, Vol 93, Num 4, pp 429-434, issn 0916-8524, 6 p.Article

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication : Dependable ComputingKITO, Nobutaka; TAKAGI, Naofumi.IEICE transactions on information and systems. 2013, Vol 96, Num 9, pp 1962-1970, issn 0916-8532, 9 p.Article

A C-Testable Multiple-Block Carry Select AdderKITO, Nobutaka; FUJII, Shinichi; TAKAGI, Naofumi et al.IEICE transactions on information and systems. 2012, Vol 95, Num 4, pp 1084-1092, issn 0916-8532, 9 p.Article

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital CircuitsOBATA, Koji; TAKAGI, Kazuyoshi; TAKAGI, Naofumi et al.IEICE transactions on electronics. 2007, Vol 90, Num 12, pp 2278-2284, issn 0916-8524, 7 p.Article

Multiple-valued-digit number representations in arithmetic circuit algorithmsTAKAGI, Naofumi.Proceedings - International Symposium on Multiple-Valued Logic. 2002, pp 224-235, issn 0195-623X, isbn 0-7695-1462-6, 12 p.Conference Paper

Systematic IEEE rounding method for high-speed floating-point multipliersQUACH, Nhon T; TAKAGI, Naofumi; FLYNN, Michael J et al.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 5, pp 511-521, issn 1063-8210, 11 p.Article

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition : Solid-State Circuit Design -Architecture, Circuit, Device and Design MethodologyNAKAMURA, Kazuhiro; SHIMAZAKI, Ryo; YAMAMOTO, Masatoshi et al.IEICE transactions on electronics. 2012, Vol 95, Num 4, pp 456-467, issn 0916-8524, 12 p.Article

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits : Superconducting signal processing technologiesTAKAGI, Kazuyoshi; ITO, Yuki; TAKESHIMA, Shota et al.IEICE transactions on electronics. 2011, Vol 94, Num 3, pp 288-295, issn 0916-8524, 8 p.Article

Bipartite modular multiplicationKAIHARA, Marcelo E; TAKAGI, Naofumi.Lecture notes in computer science. 2005, pp 201-210, issn 0302-9743, isbn 3-540-28474-5, 10 p.Conference Paper

An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuitsTAKAGI, Naofumi.Physica. C. Superconductivity. 2013, Vol 484, pp 213-216, issn 0921-4534, 4 p.Conference Paper

Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point AddersPARK, Heejoung; YAMANASHI, Yuki; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 634-639, issn 1051-8223, 6 p., 1Conference Paper

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits : Recent progress in superconductive digital electronicsTAKAGI, Naofumi; MURAKAMI, Kazuaki; FUJIMAKI, Akira et al.IEICE transactions on electronics. 2008, Vol 91, Num 3, pp 350-355, issn 0916-8524, 6 p.Article

Research on Effective Moat Configuration for Nb Multi-Layer Device StructureFUJIWARA, Kan; NAGASAWA, Shuichi; HASHIMOTO, Yoshihito et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 603-606, issn 1051-8223, 4 p., 1Conference Paper

Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm² Nb ProcessKAINUMA, Toshiki; SHIMAMURA, Yasuhiro; MIYAOKA, Fumishige et al.IEEE transactions on applied superconductivity. 2011, Vol 21, Num 3, pp 827-830, issn 1051-8223, 4 p., 1Conference Paper

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm² Nb Multi-Layer Process : Frontiers of Superconductive ElectronicsYAMANASHI, Yuki; KAINUMA, Toshiki; YOSHIKAWA, Nobuyuki et al.IEICE transactions on electronics. 2010, Vol 93, Num 4, pp 440-444, issn 0916-8524, 5 p.Article

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active LayerSATOH, Tetsuro; HINODE, Kenji; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 167-170, issn 1051-8223, 4 p., 1Conference Paper

Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths ProcessorKATAEVA, Irina; AKAIKE, Hiroyuki; FUJIMAKI, Akira et al.IEEE transactions on applied superconductivity. 2011, Vol 21, Num 3, pp 809-813, issn 1051-8223, 5 p., 1Conference Paper

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm : Frontiers of Superconductive ElectronicsTANAKA, Masamitsu; OBATA, Koji; ITO, Yuki et al.IEICE transactions on electronics. 2010, Vol 93, Num 4, pp 435-439, issn 0916-8524, 5 p.Article

A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit RepresentationTANAKA, Masamitsu; OBATA, Koji; TAKAGI, Kazuyoshi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 653-656, issn 1051-8223, 4 p., 1Conference Paper

An Operand Routing Network for an SFQ Reconfigurable Data-Paths ProcessorKATAEVA, Irina; AKAIKE, Hiroyuki; FUJIMAKI, Akira et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 665-669, issn 1051-8223, 5 p., 1Conference Paper